Embodiments of the present invention relate to a semiconductor memory device, and more specifically to a semiconductor memory device including an open bit line structure and a method of testing the semiconductor memory device.
Generally, as a degree of the integration of a semiconductor memory device such as a Double Data Rate Synchronous DRAM (DDR SDRAM) device has been rapidly increased, the semiconductor memory device has been designed to include tens of millions of memory cells therein.
A memory cell structure of the semiconductor memory device is classified into a folded bit line structure and an open bit line structure. A difference between the folded bit line structure and the open bit line structure will hereinafter be described in detail.
In the folded bit line structure, a bit line, e.g., a true bit line, where data is driven and a bit line, e.g., a false bit line, used as a reference in an operation of amplifying the driven data are arranged in the same memory cell mat on the basis of a bit line sense amplifier arranged in a core region of the semiconductor memory device.
As a result, the same noise is reflected on the true bit line and the false bit line, and noise generated in the true bit line and noise generated in the false bit line are counterbalanced with each other. Through the counterbalancing operation, the folded bit line structure can guarantee stable operations irrespective of noise.
On the other hand, in the open bit line structure, a true bit line and a false bit line are arranged in different memory cell mats on the basis of a bit line sense amplifier. Therefore, noise generated in the true bit line is different from noise generated in the false bit line, and thus the open bit line structure is vulnerable to such noise.
A unit memory cell structure for use in the folded bit line structure has been designed in 8F2, and a unit memory cell structure for use in the open bit line structure has been designed in 6F2.
The unit memory cell structure is used as an important element for deciding the size of the semiconductor memory device. Assuming the same data storage amount, a semiconductor memory device including the open bit line structure can be designed to be smaller than a semiconductor memory device including the folded bit line structure.
FIG. 1 illustrates a circuit diagram of a memory cell array including a general folded bit line structure.
In FIG. 1, reference numbers 10 and 11 indicate memory cell mats, and a reference number 12 indicates a sense-amplifier region disposed between the memory cell mats 10 and 11. The memory cell array is generally composed of a plurality of memory cell mats and sense-amplifier regions.
In FIG. 1, bit lines BLT0A, BLB0A, BLT1A, BLB1A, BLT2A, and BLB2A and bit lines BLT0B, BLB0B, BLT1B, BLB1B, BLT2B, and BLB2B indicate bit lines coupled to memory cell transistors (not shown) in the memory cell mats 10 and 11, respectively.
A bit line equalizing signal BLEQB is a control signal for equalizing the bit lines with equal potential. Control signals SHL and SHR connect the bit lines to the sense-amplifier region. A bit line precharge voltage VBLP is a precharge voltage for precharging the bit lines.
Drive signals CSP or CSN indicate drive voltages of a sense amplifier. A column selection signal YS is a signal for selecting an internal column address. Local input/output lines LIO and LIOB are lines used for receiving data from bit lines selected by the column selection signal YS and transmitting the received data to an external part.
However, as a bit line structure of the semiconductor memory device is changed from the folded bit line structure to the open bit line structure, the true bit line BL and the false bit line BLB are disposed in different memory cell mats.
If the true bit line BL and the false bit line BLB that are used to operate the same sense amplifier are located in different memory cell mats, a noise effect is different in the true bit line BL and the false bit line BLB during a sensing operation.
FIG. 2 illustrates a write recovery (tWR) test for use in a conventional semiconductor memory device.
Referring to FIG. 2, upon receiving data from an external part in response to a write command WT, a column selection signal Yi is enabled to a high level. As a result, under the condition that a word line WL is enabled to a high level, external data is written in a selected cell.
FIG. 2 shows that low data is newly received from the external part under the condition that high data is stored in the selected cell.
In this case, a time difference between an activation time of the write command WT and that of a precharge command PCG is defined as a write recovery (tWR) time. The tWR time is used as an index for estimating write characteristics.
According to the conventional tWR test shown in FIG. 2, it is determined whether or not the external data is correctly written in the selected cell by mandatorily reducing the tWR time.
That is, since the tWR time is very short, data stored in the selected cell is not changed from the previously stored high data to the low data received from the external part and thus it maintains the high data, such that the selected cell is determined as failed in a probe test.
The above-mentioned tWR test is used to screen a cell having poor write characteristics as the cell has resistance Rc at a high level, a threshold voltage Vt at a high level, or capacitance Cs at a low level.
However, in case of a cell having high cell resistance, e.g., contact resistance, channel resistance, etc., there is a probability that a failed cell is not screened even in the same tWR time as in a normal cell and thus is wrongly considered to be the normal cell.
In case of a cell having high cell resistance Rc, a small amount of charges is applied to a storage node SN due to such resistance, such that it is impossible to sufficiently write high data in the cell during a normal write operation. As a result, a write operation for writing low data in a cell storing high data can be easily achieved even with a reduced tWR time. That is, assuming that charges greater than an offset of a sense amplifier are guaranteed, the cell having high resistance can also pass the tWR test without any problems.
In conclusion, a high-resistance cell to be determined to be a failed cell can unexpectedly pass the tWR test. If the tWR time is excessively reduced to screen such defective cells, even normal cells may wrongly be over-screened.